Classification and transformation of dynamic dataflow programs

International audienceDataflow programming has been used to describe signal processing applications for many years, traditionally with cyclostatic dataflow (CSDF) or synchronous dataflow (SDF) models that restrict expressive power in favor of compile-time analysis and predictability. Dynamic dataflow is not restricted with respect to expressive power, but it does require runtime scheduling in the general case. Fortunately, most signal processing applications are far from being entirely dynamic, and parts with static behavior need not be dynamically scheduled. This paper presents a method to automatically analyze and classify blocks of a dynamic dataflow program within more restrictive dataflow models when possible, and to transform the blocks classified as static to improve execution speed by reducing the number of FIFO accesses. We used this method on actors of two dynamic dataflow descriptions of an MPEG-4 part 2 decoder, and study how classification and transformation increases decoding speed

Classification of Dataflow Actors with Satisfiability and Abstract Interpretation

International audienceDataflow programming has been used to describe signal processing applications for many years, traditionally with cyclo-static dataflow (CSDF) or synchronous dataflow (SDF) models that restrict expressive power in favor of compile-time analysis and predictability. More recently, dynamic dataflow is being used for the description of multimedia video standards as promoted by the RVC standard (ISO/IEC 23001:4). Dynamic dataflow is not restricted with respect to expressive power, but it does require runtime scheduling in the general case, which may be costly to perform on software. The authors presented in a previous paper a method to automatically classify actors of a dynamic dataflow program within more restrictive dataflow models when possible, along with a method to transform the actors classified as static to improve execution speed by reducing the number of FIFO accesses (Wipliez & Raulet, 2010). This paper presents an extension of the classification method using satisfiability solving, and details the precise semantics used for the abstract interpretation of actors. The extended classification is able to classify more actors than what could previously be achieved

Software Code Generation for the RVC-CAL Language

International audienceThe MPEG Reconfigurable Video Coding (RVC) framework is a new standard under development by MPEG that aims at providing a unified high-level specification of current and future MPEG video coding technologies using dataflow models. In this framework, a decoder is built as a configuration of video coding modules taken from the standard MPEG toolbox library or proprietary libraries. The elements of the library are specified by a textual description that expresses the I/O behavior of each module and by a reference software written using a subset of the CAL Actor Language named RVC-CAL. A decoder configuration is written in an XML dialect by connecting a set of CAL modules. Code generators are fundamental supports that enable the direct transformation of a high level specification to efficient hardware and software implementations. This paper presents a synthesis tool that from a CAL dataflow program generates C code and an associated SystemC model. The generated code is validated against the original CAL description simulated using the Open Dataflow environment. Experimental results of the translation of two descriptions of an MPEG-4 Simple Profile decoder with different granularities are shown and discussed

Efficient multicore scheduling of dataflow process networks

International audienceAlthough multi-core processors are now available everywhere, few applications are able to truly exploit their multiprocessing capabilities. Dataflow programming attempts to solve this problem by expressing explicit parallelism within an application. In this paper, we describe two scheduling strategies for executing a dataflow program on a single-core processor. We also describe an extension of these strategies on multi-core architectures using distributed schedulers and lock-free communications. We show the efficiency of these scheduling strategies on MPEG-4 Simple Profile and MPEG-4 Advanced Video Coding decoders

A portable Video Tool Library for MPEG Reconfigurable Video Coding using LLVM representation

International audienceMPEG Reconfigurable Video Coding (RVC) represents the last answer of MPEG to overcome the lack of interoperability between codecs deployed in the market nowadays. The main goal of MPEG RVC is to provide a set of coding tools employed in all MPEG standards, the Video Tools Library (VTL), encapsulated into independent entities called Functional Units (FUs). FUs are described as dataflow actors in RVC-CAL actor language (RVC-CAL) and decoders are described as dataflow programs with the Abstract DecoderModels (ADMs). Therefore, an ADM of an MPEG decoder corresponds in MPEG RVC to a network of FUs taken from the VTL. The typical use of MPEG RVC is to translate an ADM into a hardware or software description language that target one specific platform. In [1], we propose to skip this synthesis process of ADM and to directly integrate a portable version of VTL described in the Low-Level Virtual Machine Intermediate Representation (LLVM IR) inside platforms. This portable VTL is couple with a new RVC Decoder, we called Just-In-Time Adaptive Decoder Engine (Jade), that dynamically instantiates ADM to decode any encoded video using its associated network description. In this paper, we introduce the different compiling steps required to obtain an automatically translation of a VTL described in RVC-CAL into a portable VTL described in LLVM. This translation is based on a new RVC-CAL compiler called Open RVC-CAL Compiler (Orcc)

LLVM-based and scalable MPEG-RVC decoder

WOSInternational audienceMPEG reconfigurable video coding (RVC) is a new platform-independent specification methodology chosen by the MPEG community for describing coding standards. This methodology aims at producing abstract decoder models (ADMs) of MPEG decoders as programs described in a dataflow language namely "RVC-CAL Actor Language" (RVC-CAL). RVC-CAL naturally expresses potential parallelism between tasks of an application, which makes an ADM description suitable for implementation to a wide variety of platforms, from uniprocessor systems to FPGAs. MPEG RVC eases the development process of decoders by building decoders at a library-component level instead of using monolithic algorithms, and by providing a library of coding tools standardized in MPEG. This paper presents new mechanisms based on the low level virtual machine that allow the conception of a decoder able to dynamically instantiate several RVC decoder descriptions. This decoder, unlike static decoders generated by RVC tools, keeps de facto the features of an RVC description namely portability, scalability and reconfigurability

Reconfigurable video coding: a stream programming approach to the specification of new video coding standards

International audienceCurrent video coding standards, and their reference implementations, are architected as large monolithic and sequential algorithms, in spite of the considerable overlap of functionality between standards, and the fact that they are frequently implemented on highly parallel computing platforms. The former leads to unnecessary complexity in the standardization process, while the latter implies that implementations have to be rebuilt from the ground up to reflect the parallel nature of the target. The upcoming Reconfigurable Video Coding (RVC) standard currently developed at MPEG attempts to address these issues by building a framework that supports the construction of video standards as libraries of coding tools. These libraries can be incrementally updated and extended, and the tools in them can be aggregated to form complete codecs using a streaming (or dataflow) programming model, which preserves the inherent parallelism of the coding algorithm. This paper presents the RVC framework and its underlying data flow programming model, along with the tool support and initial results

Generation of Efficient High-Level Hardware Code from Dataflow Programs

High-level synthesis (HLS) aims at reducing the time-to-market by providing an automated design process that interprets and compiles high-level abstraction programs into hardware. However, HLS tools still face limitations regarding the performance of the generated code, due to the difficulties of compiling input imperative languages into efficient hardware code. Moreover the hardware code generated by the HLS tools is usually target-dependant and at a low level of abstraction (i.e. gate-level). A generated code at a high-level of abstraction (i.e. chip-level) is better suited to the needs of systems' architects because they can understand and control all of the design processes. We propose in this paper a new approach to HLS to generate efficient, high-level hardware code from Dataflow Programs. Implementation results (from two dynamic dataflow programs) on Xilinx, Altera and Latice FPGAs and on ASIC targeting 90nm CMOS technology are also presented

Multi-Purpose Systems: A Novel Dataflow-Based Generation and Mapping Strategy

International audienceThe Dataflow Process Networks (DPN) Model of Computation (MoC) has been used in di ferent ways to improve time-to-market for complex multi-purpose systems. The development of such systems presents mainly two problems: (1) the manual creation of the multi-purpose specialized hardware infrastructures is quite error-prone and may take a lot of time for debugging; (2) the more hardware are the details to be handled the greater the eff ort required to define an optimized components library. This paper tackles both problems, leveraging on the combination of the DPN MoC with a coarse-grained recon gurable approach to hardware design and on the exploitation of the DPN MoC for the synthesis of target-independent hardware codes. Combining two state of the art tools, namely the Multi-Dataflow Composer tool and the Open RVC-CAL Compiler, we propose a novel dataflow-based design ow that provide a considerable on-chip area saving targeting both FPGAs and ASICs

Fast Hardware implementation of an Hadamard Transform Using RVC-CAL Dataflow Programming

International audienceImplementing an algorithm to hardware platforms is generally not an easy task. The algorithm, typically described in a high-level specification language, must be translated to a low-level HDL language. The difference between models of computation (sequential versus fine-grained parallel) limits the efficiency of automatic translation. On the other hand, manual implementation is time-consuming, because the designer must take care of low level details, and write test benches to test the implementation's behavior. This paper presents a global design method going from high level description to implementation. The first step consists in describing an algorithm as a dataflow program with the RVC-CAL language. Next step is the functional verification of this description using a software framework. The final step consists in an automatic generation of an efficient hardware implementation from the dataflow program. The objective was to spend the most part of the conception time in an open source software platform. We used this method to quickly prototype and generate hardware implementation of the Hadamard transform, an algorithm used in many signal processing algorithms, from an RVC-CAL description